(a) Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a semiconductor device for forming a source/drain region of an analog CMOS.
(b) Description of the Related Art
Generally, transistors of semiconductor devices may be classified into an NMOS, a PMOS, and a CMOS according to their channel type. An NMOS is formed with an N-channel, and a PMOS with a P-channel. In addition, the CMOS (complementary metal oxide silicon) has the NMOS and the PMOS, and thus both an N-channel and a P-channel are formed therein.
A conventional CMOS manufacturing method will hereinafter be described in detail with reference to FIG. 1A to FIG. 1D.
FIG. 1A to FIG. 1D are cross-sectional views showing principal manufacturing stages of a conventional semiconductor device.
As shown in FIG. 1A, a well 2 is formed on a semiconductor substrate 1 by implanting ions, and a field oxide layer 3 is formed thereon. The well 2 is classified as a p-well or an n-well according to the type of ions implanted into the semiconductor substrate 1. The p-well is formed on a semiconductor substrate for forming an NMOS, and the n-well is for forming a PMOS.
Then, as shown in FIG. 1B, a gate oxide layer 4 is formed on the semiconductor substrate 1. Subsequently, a conductive layer such as a polysilicon layer is formed on the field oxide layer 3 and gate oxide layer 4, and it is patterned by a photolithography and etching process so as to form a first capacitor electrode 5b and a gate electrode 5a of an analog CMOS.
As shown in FIG. 1C, a capacitor dielectric layer 6 such as an oxide-nitride-oxide (ONO) layer is formed on the first capacitor electrode 5b, and a second capacitor electrode 7b is formed thereon so as to form a capacitor stack. Subsequently, impurity ions are implanted at a low concentration into the semiconductor substrate 1 using the gate electrode 5a as an implantation mask.
Then, as shown in FIG. 1D, spacer layers 10a and 10b are respectively formed on sidewalls of the gate electrode 5a and sidewalls of the capacitor stack. Subsequently, impurity ions are implanted at high concentrations into the semiconductor substrate 1 using the gate electrode 5a and the insulation layer spacer 10a as an implantation mask. Then, a source region 8a, a drain region 8b, and lightly doped drain (LDD) regions 9a and 9b are formed. The lightly doped drain regions 9a and 9b are located between the source/drain regions 8a, 8b and a channel region, and are used for suppressing device degradation such as a hot carrier effect.
As described above, in order to form the conventional lightly doped drain regions 9a/9b and the source/drain regions 8a/8b, the ion implantation process for forming a source/drain should be performed at least twice.
The above information described in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that is not prior art to the present invention.